Mixed Implementations
Digital designs implemented in VHDL and SystemVerilog
Integrated Circuits modeled in System Description Languages such as SystemC or SystemVerilog
Integrated Circuits simulated with open source tools such as Verilator (SystemC / SystemVerilog)
Integrated Circuits verified using Universal Verification Methodology
Integrated Circuits described in traditional Hardware Description Languages such as VHDL or Verilog
Integrated Circuits simulated with open source tools such as GHDL (VHDL) or Icarus Verilog (Verilog)
Integrated Circuits synthesized with open source tools such as Yosys (Verilog)
Integrated Circuits optimized with open source tools such as ABC
Integrated Circuits verified with open source tools such as SymbiYosys and using Formal Verification
Integrated Circuits floor-planned with open source tools such as Magic and using open standard cells
Integrated Circuits placed with open source tools such as Graywolf and using open standard cells
Integrated Circuits timing-analyzed with open source tools such as STA and using open standard cells
Integrated Circuits routed with open source tools such as Qrouter and using open standard cells
Integrated Circuits simulated with open source tools such Irsim and using open standard cell
Integrated Circuits verified with open source tools such Netgen LVS and using open standard cells
Integrated Circuits checked with open source tools such Magic DRC and using open standard cells
Integrated Circuits printed with open source tools such as Magic GDS and using open standard cells
Printed Circuit Board Schematic Diagrams drawn with open source tools such as KiCad or gEDA
Printed Circuit Board Mask Layouts printed with open source tools such as KiCad or gEDA
Printed Circuit Board Mask Layouts verified with open source tools such as KiCad or gEDA
Printed Circuit Board and Integrated Circuit Mask Layouts tested with open source tools such as KiCad or gEDA
Integrated Circuits (ASIC & FPGA) described in VHDL & Verilog; verified and synthesized with open source tools; and printed with open standard cells.
Printed Circuits Boards drawn, printed, verified and tested with open source tools.
Digital designs implemented in VHDL and SystemVerilog.
Digital designs simulated and verified using universal and formal methods.
Open Source Hardware Descriptions and Open Source Tools used.