Tokyo (Japan) Nishitōkyō
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pacoreinacampo@queenfield.tech Text

Developing at QueenField

Integrated Circuits (ASIC & FPGA) described in VHDL & Verilog; verified and synthesized with open source tools; and printed with open standard cells.

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Modeling System ICs

Integrated Circuits modeled in System Description Languages such as SystemC or SystemVerilog

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Simulating System ICs

Integrated Circuits simulated with open source tools such as Verilator (SystemC / SystemVerilog)

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Verifying System ICs

Integrated Circuits verified using Universal Verification Methodology

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Describing RTL ICs

Integrated Circuits described in traditional Hardware Description Languages such as VHDL or Verilog

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Simulating RTL ICs

Integrated Circuits simulated with open source tools such as GHDL (VHDL) or Icarus Verilog (Verilog)

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Synthesizing RTL ICs

Integrated Circuits synthesized with open source tools such as Yosys (Verilog)

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Optimizing RTL ICs

Integrated Circuits optimized with open source tools such as ABC

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Verifying RTL ICs

Integrated Circuits verified with open source tools such as SymbiYosys and using Formal Verification

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Planning Switch ICs

Integrated Circuits floor-planned with open source tools such as Magic and using open standard cells

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Placing Switch ICs

Integrated Circuits placed with open source tools such as Graywolf and using open standard cells

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Timing Switch ICs

Integrated Circuits timing-analyzed with open source tools such as STA and using open standard cells

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Routing Switch ICs

Integrated Circuits routed with open source tools such as Qrouter and using open standard cells

XIII
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Simulating Switch ICs

Integrated Circuits simulated with open source tools such Irsim and using open standard cell

XIV
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Verifying Switch ICs

Integrated Circuits verified with open source tools such Netgen LVS and using open standard cells

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Checking Switch ICs

Integrated Circuits checked with open source tools such Magic DRC and using open standard cells

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Printing Switch ICs

Integrated Circuits printed with open source tools such as Magic GDS and using open standard cells

Printed Circuits Boards drawn, printed, verified and tested with open source tools.

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Drawing PCBs

Printed Circuit Board Schematic Diagrams drawn with open source tools such as KiCad or gEDA

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Printing PCBs

Printed Circuit Board Mask Layouts printed with open source tools such as KiCad or gEDA

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Verifying PCBs

Printed Circuit Board Mask Layouts verified with open source tools such as KiCad or gEDA

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Testing ICs+PCBs

Printed Circuit Board and Integrated Circuit Mask Layouts tested with open source tools such as KiCad or gEDA

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Why Choose QueenField

More than 5 year experience in Hardware and Software Systems

Integrated Circuits (ASIC & FPGA) described in VHDL & Verilog; verified and synthesized with open source tools; and printed with open standard cells.

Printed Circuits Boards drawn, printed, verified and tested with open source tools.

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Mixed Implementations

Digital designs implemented in VHDL and SystemVerilog.

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UVM-OSVVM and Formal Verification

Digital designs simulated and verified using universal and formal methods.

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100% Open Hardware

Open Source Hardware Descriptions and Open Source Tools used.

Philosophy

Implementing Integrated Circuits from RTL to GDS and Testing with Printed Circuit Boards

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Mixed Implementations

Digital designs implemented in VHDL and SystemVerilog

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UVM-OSVVM and Formal Verification

Digital designs simulated and verified using universal and formal methods

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100% Open Hardware

Open Source Hardware Descriptions and Open Source Tools used