Chronology
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Higashi-Fushimi - Nishitokyo (Tokyo)
FINTECH
QueenField in Asia
from RTL to GDS
with Open Source Tools and Open Standard CellsDeveloping Hardware and Software Worldwide
QueenField Japan 2020.2
Developing MPSoC-RISCV in Tokyo
QueenField Japan 2020.1
Developing MPSoC-OR1K in Tokyo
QueenField Japan 2020.1
Developing MPSoC-MSP430 in Tokyo
QueenField Spain 2019.2
Developing MPSoC-DBG in Santander
QueenField Spain 2019.2
Developing MPSoC-UART in Santander
QueenField Spain 2019.2
Developing MPSoC-MPI in Santander
QueenField Spain 2019.2
Developing MPSoC-DMA in Santander
QueenField Spain 2019.1
Developing MPSoC-MSI in Santander
QueenField Spain 2019.1
Developing MPSoC-MPRAM in Santander
QueenField Spain 2019.1
Developing MPSoC-SPRAM in Santander
QueenField Spain 2019.1
Developing MPSoC-GPIO in Santander
QueenField Spain 2019.1
Developing MPSoC-NoC in Santander
QueenField Ireland 2018.2
Developing SoC-RISCV in Cork
QueenField Ireland 2018.1
Developing PU-RISCV in Cork
QueenField Brazil 2017.2
Developing vhdl2verilog in Florianopolis
QueenField Brazil 2017.1
Developing verilog2vhdl in Florianopolis
QueenField Brazil 2016.2
Developing SoC-OR1K in Joinville
QueenField Brazil 2016.1
Developing SoC-MSP430 in Joinville
QueenField Spain 2015.2
Developing PU-OR1K in Seville
QueenField Spain 2015.1
Developing PU-MSP430 in SevilleProcedural
Building open source hardware devices based on mixed implementations (VHDL & SystemVerilog) using open source tools.
Academic
Building hardware devices based on the Scientific Method, seeking to minimize the influence of subjectivity at work, reinforcing the validity of the results.
Universal
Building hardware devices with formal verification and traditional simulation including the standard features only.
Modeling, Describing, Simulating (System Level, RTL, Switch Level), Verifying (System Level, RTL, Switch Level), Synthesizing, Optimizing, Planning, Placing, Timing, Routing, Checking and Printing Electronic Circuits.
Front-End Solutions
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