Placing Switch Level of Hardware
Solutions / Graywolf
Standard Cell Placer
A Standard Cell Placer takes a given synthesized circuit netlist together with a technology library and produces a valid placement layout. The layout is optimized according to the aforementioned objectives and ready for cell resizing and buffering, a step essential for timing and signal integrity satisfaction. Physical design flow are iterated a number of times until design closure is achieved.
Modeling, Describing, Simulating (System Level, RTL, Switch Level), Verifying (System Level, RTL, Switch Level), Synthesizing, Optimizing, Planning, Placing, Timing, Routing, Checking and Printing Electronic Circuits.
Front-End Solutions
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