Master Slave Interface for Multi-Processor System on Chip
Products / MPSoC-MSI
Master Slave Interface
A Master Slave Interface (MSI) is a model of communication where one device has unidirectional control over other devices. A master is selected from a group of eligible devices, with the other devices acting in the role of slaves. The ARM Advanced Microcontroller Bus Architecture (AMBA) and Wishbone Bus are an open-standard, on-chip interconnect specification for the connection and management of functional blocks.
Work: Implementation in VHDL & (System)Verilog of a Master Slave Interface and simulation in GHDL & Icarus Verilog
Modeling, Describing, Simulating (System Level, RTL, Switch Level), Verifying (System Level, RTL, Switch Level), Synthesizing, Optimizing, Planning, Placing, Timing, Routing, Checking and Printing Electronic Circuits.
Front-End Solutions
Copyright © All rights reserved | This web is made by PacoReinaCampo