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Procedural
Building open source hardware devices based on mixed implementations (VHDL & SystemVerilog) using open source tools.
Academic
Building hardware devices based on the Scientific Method, seeking to minimize the influence of subjectivity at work, reinforcing the validity of the results.
Universal
Building hardware devices with formal verification and traditional simulation including the standard features only.
Modeling, Describing, Simulating (System Level, RTL, Switch Level), Verifying (System Level, RTL, Switch Level), Synthesizing, Optimizing, Planning, Placing, Timing, Routing, Checking and Printing Electronic Circuits.
Front-End Solutions
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